基于bist的嵌入式存储器可测性设计研究-电路与系统专业论文.docxVIP

ABSTRACTABSTRACT：Now,embedded ABSTRACT ABSTRACT：Now,embedded memory has been taking more and more proportions in system—on-a-chip(SoC)，which has become a remarkable character for SoC．With the high density,embedded memory is much easier to result in fault than any other components on the chip，has become a important factor to the yielding chip．Now,chip testing issue has become a bottleneck restricting the scale of the integrate circuit．The conventional Auto Test Equipments can not meet the test demand of very large scale integrate circuit． The BIST(Build—In Self-Test)method has been used in the memory test．The key problem to the BIST is the fault model，effective algorithm and implement． First of all，the thesis researches the theory to DFT(Design For Test)of system chips，gives a deeper research to BIST in DFT,analyses the main methods of embedded memory test and their characteristics，particularly researches the MBIST(Memory BIST)．Then analyses the fault model of embedded memory and the common faults and the popular test algorithms of embedded memory,compares their fault coverage，particularly researches the pseudorandom test algorithm and the March algorithm． The thesis designs a pseudorandom generator,which is carried out with LFSR，achieves the weighted FSR and ergodic FSR by improving the LFSR．The design is programmed using Verilog HDL and simulated by Modelsim． The thesis works out a improvable MBIST design with the function of fault checking and debugging．We use the March C+algorithm which has high fault coverage，design the MBIST based on FSM(Finite State Machine)．We program the SRAM model with Verilog HDL and inject kinds of faults to the SRAM．The whole design is simulated by Modelsim．The design Can accurately find the address which has fault and judge the fault type． Experimentation has proved that the MBIST design presented by this paper is practicable．It Can detect and debug the faults of embedded memory with less test time and high fault coverage．The embedded