基于 fpga 局部动态可重构技术的可靠性系统实现与优化-软件工程专业论文.docxVIP

摘要 摘要 摘要 随着半导体工艺技术的不断发展，基于 SRAM 的 FPGA 芯片内部的硬件逻辑 资源规模不断扩大，因此对其可靠性要求也不断提高。三模冗余技术是一种由三 个完全相同的复制电路模块及一个多数表决器构成的具有容错功能的电路结构， 该技术可以为系统电路提供较高的可靠性，但需要使用大量的额外硬件资源实现， 造成面积冗余问题。 局部动态可重构技术是一种可以实时修改 FPGA 中局部电路功能，并且不会 影响其电路其它部分的新技术。将局部动态可重构技术应用到传统的三模冗余结 构电路中，可以有效地解决面积冗余问题，然而由于该方法需要额外的重构配置 时间进行重构过程，会造成时间冗余问题。 为了解决局部动态可重构技术所带来的时间冗余问题，本文提出了一种全新 的先行重构配置算法，该算法核心思想是利用一个额外的可重构区域，在当前电 路工作在第一个可重构区域中时，将下一时刻需要的电路配置到第二个可重构区 域中。对基于先行重构配置算法的三模冗余电路进行分析，并与传统的三模冗余 结构电路进行比较。实际电路的实验结果表明，该方法在为系统电路提供较高可 靠性的同时，可以有效地解决由局部动态可重构技术带来的时间冗余问题。 关键词： 可靠性 三模冗余技术 局部动态可重构技术 先行重构配置算法 FPGA ABSTRACT ABSTRACT ABSTRACT With the highly developed Semiconductor technology, the scale of the hardware logic resources on the SRAM based FPGA was increased, so the high dependability system of FPGA is necessary. Triple Modular Redundancy (TMR) technique is a common structure using three duplications of original circuit and a majority voter mechanism to implement the high fault tolerant ability, which provides system the high reliability, but due to the required of a large numbers of extra hardware logic resources for the implementation, the TMR method will suffers from the area overhead problem. Partial reconfiguration technique is an advanced technology that can reconfigure a portion of a FPGA while the other part won’t be affected. By applying the partial reconfiguration technique into a common TMR structure, it can improve the area efficiency of the system. However, this method will bring the time overhead due to the reconfiguration time. To deal with the time overhead problem, an optimized configuration look-ahead partial reconfiguration TMR structure has been proposed, which use an additional reconfigurable partition to configure the next reconfigurable module while the current reconfigurable module is working in the first reconfigurable partition. The result of experiment shows that the proposed partial reconfiguration TMR structure with reconfiguration look-ahead mechanism can reduce the area utilization compare t