《基于FPGA的解码器的设计的英文原文及翻译》-毕业设计（论文）.docVIP

附录 一、英文全文 A New Design of HDB3 Encoder and Decoder Based on FPGA Yang Zhang, Xiumin Wang College of Information Engineering China Jiliang University Hangzhou, Yuduo Wang School of Optoelectronic Information Telecommunication Engineering Beijing Informaton ScienceTechnology University Abstracts A new design of HDB3 encoder and decoder based on FPGA is proposed to deal with the high complexity and long output delay of the encoder and no error correction function of the decoder which have been implemented so far. The encoder has the function of converting a NRZ code sequence to a HDB3 sequence and the decoder, vice versa. Meanwhile the decoder can correct the errors in the received HDB3 sequence according to a certain rule. Synthesis reports show that the encoder and decoder are both simple-structured; Simulation results show that the encoder has a shorter output delay and the decoder has a better function of error detecting ,and correcting which greatly improves the reliability of the system. Keywords HDB3 encoder decoder Verilog HDL FPGA INTRODUCTION HDB3 code is an improved version of AMI code. It has all the advantages of AMI code i.e. error detection function[l], no DC component, narrow energy spectrum. Besides it overcomes the difficulty of extracting timing signal when there is a long sequence of 0s in the message to be transmitted. So it has been widely applied to the data transmission of high density information flow and recommended as the interface pattern in the digital transmission of base group, secondary group and third group [2,3] by the CCITT G 703.Today the I-IDB3 encoders and decoders are mainly realized by ASIC and peripheral small and medium-sized chips, the structures of which are all complex. To overcome this defect, a new implementation approach which is based on FPGA is proposed .The structures of the encoder and decoder are both simple. Besides the decoder has the function of error detecting and correcting as well as decoding. When ther