等离子体干法刻蚀低介电常数绝缘材料的主要问题与解决办法-材料工程专业论文.pdf.docxVIP

摘 摘 要 随着高集成度的超大规模电路的飞速发展，器件尺寸逐渐缩 小，RC延迟成为除器件的特征尺寸外决定器件功能的最主要因素之 一。RC延迟大致正比于导线的电阻率和绝缘介质的介电常数。要降 低电阻率，可采用铜导线来取代铝；而要降低介电常数，则必须采 用低介电常数的绝缘材料，即Low-k材料。要降低绝缘材料的介电 常数就必须减少材料内部极化键的数目，并且降低材料的密度。与 此同时带来的主要问题就是低介电常数材料的机械强度大大降低， 材料组成的变化也将给干法刻蚀带来许多未曾遇到过的新问题。 本论文通过干法去胶工艺菜单刻蚀介电常数为2．6的绝缘材料 的实验，探究如何在等离子体干法刻蚀低介电常数材料的时候保持 各向异性和所需要的选择比，避免缺陷以及其他因为材料特性变化 带来的新问题的方法。通过分析等离子体干法刻蚀对低介电常数材 料造成损伤的机理，实验寻找出对损伤或缺陷影响最大的一些工艺 参数，如气体种类、压力、射频频率、功率等等。在掌握了以上工 艺参数对Low-k材料损伤的影响规律之后，将其应用到40nm双大 马士革无中间层沟槽工艺中对低介电常数材料BD的等离子体干法 刻蚀，达到尽量减少低介电常数材料损伤或缺陷，并且满足其他工 艺要求的目的。 关键词：等离子体干法刻蚀、低介电常数材料、RC延迟、侧壁损伤、 40nm沟槽刻蚀 AbstractWith Abstract With the rapid development of high level integrat ion of VLSI Circuits，the device dimensions narrows gradualIF．RC delay became the characteri st iC dimensions in the device of the main functions of decision devices． RC delay iS roughly proportional to the resistivity of the wires and dielectric permittivity．To reduce the resistivity，Copper can be used to replace Aluminum wires．And to reduce the dielectric constants，low dielectric constant of insulating materials， namely low—k materialS，must be used．To reduce the dielectriC constants of insulation material，the number of key polarization， and the density of material must be reduced． Meanwhi 1e the main problem iS low dielectriC constant of material mechanical strength greatly reduced．Material composition change will also give dry etching a lot of new problems which have never met before． This paper is based on the experiment of plasma etching low——k material(k value 2．6)，explores the approaches to solve the new problems fol lowed with material property changing when plasma dry etching low—k material， such as keeping ani sotropic and needed selectivity，avoiding defects，etc． Through the analysis of plasma dry etching low—’k material damage mechanism of injury，find out some of the biggest influence defects or process parameters，such as gas species， pressure，RF frequency and power，etc．In the mastery of low—k damage process trend of the