达芬奇系统简介.ppt

达芬奇及EVM 板原理图介绍 达芬奇＝DSP64X+ 内核 ＋ARM 9 内核 1.DSP核内部结构（可通过BIOS分配大小） 32K L1 Program RAM/CACHE 80K L1 Data RAM/CACHE 64K L2 Unified Mapped RAM/CACHE 2.ARM9 内核 32 BIT ARM 指令 、16 BIT Thumb 指令 16K 指令CACHE，8K 数据 CACHE 16K RAM，8K ROM DSP 和 ARM 均小端模式 3. 视频处理子系统 ：视频前端和视频后端 先介绍下DSP 子系统 DSP子系统 DSP 内核为标准的TI的TMS320C64x+ 模块和 L1P, L1D, and L2 Features of the C6000： 1.Advanced VLIW CPU with eight functional units, including two multipliers and six arithmetic units 2. Instruction packing 3. Conditional execution of most instructions 4. Efficient code execution on independent functional units 5. 8/16/32-bit data support, providing efficient memory support for a variety of applications 6.40-bit arithmetic options add extra precision for vocoders and other computationally intensive applications 7. Saturation and normalization provide support for key arithmetic operations 8. Field manipulation and instruction extract, set, clear, and bit counting support a common operation found in control and data manipulation applications additional features of the C6000： 1. Each multiplier can perform two 16 ′ 16-bit or four 8 ′ 8-bit multiplies every clock cycle 2. Quad 8-bit and dual 16-bit instruction set extensions with data flow support 3. Support for nonaligned 32-bit (word) and 64-bit (double word) memory accesses 4.Special communication-specific instructions to address common operations in error-correcting codes 5. Bit count and rotate hardware extends support for bit-level algorithms 6. Compact instructions: common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce code size 7. Protected mode operation: a two-level system of privileged program execution to support higher capability operating systems and system features, such as memory protection 8. Exceptions support for error detection and program redirection to provide robust code executi