学术会议告模板-nas-conference.org.ppt

Shouqing Hao Institute of Computing Technology, Chinese Academy of Sciences haoshouqing@ict.ac.cn Processes Scheduling on Heterogeneous Multi-core Architecture with Hardware Support Contents Introduction Hardware support for LLC-miss latency LA-ACMP scheduling algorithm Evaluation and analysis Introduction Heter-CMP: Heterogeneous Chip Multi-Processor Composed with some big cores and some small cores Big cores: large area, high power, high performance Adapted to CPU-bound programs, serial programs, …… Small cores: Small area, low power, low performance Adapted to memory-bound programs, parallel programs, …… Advantage Make good use of chip resources Reduce power and performance waste Challenge Identify applications’ behaviors when executing Schedule proper programs to proper cores Hardware Support (1) Identify programs’ behaviors Last level cache (LLC) miss latency LLC miss ? Memory access Memory accesses induce high latency Affect programs’ efficiency when executed Can not make full use of cores’ performance Schedule rules Programs with high LLC miss latency should be scheduled to small cores Programs with low LLC miss latency should be scheduled to big cores Hardware Support (2) Identify programs’ behaviors Last level Cache (LLC) miss latency Mechanism LLC miss delay is the period between miss request and miss response UN-Overlapped, Overlapped Record LLC miss latency for each core, with hardware support Hardware Support (3) Implemented based on Godson-3A Record LLC miss request and response for each core, with hardware support Hardware Support (4) LA-ACMP Schedule Algorithm(1) LA-ACMP：Latency-Aware Asymmetry CMP Identify heterogeneity of cores Based on Linux kernel 2.6.18 Calculate BogoMIPS value of each core, evaluate each core’s performance Workload assignment balance Using Scaled Load method L=N/P: each core’s scaled load N: number of workloads being in queue P: processor’s performance If Lmax – Lmin = 1, workload assignment balan