用D触发器实现2倍分频的Verilog描述-与非网-EEFOCUS.DOC

用D触发器实现2倍分频的Verilog描述？ module divide2( clk , clk_o, reset); input clk , reset; output clk_o; wire in;reg out ; always @ ( posedge clk or posedge reset) if ( reset) out = 0; else out = in; assign in = ~out; assign clk_o = out; endmodule 用verilog实现分频的一点心得2007-0