基于EDA工具的标准单元低功耗设计方法研究-电子与通信工程专业论文.docxVIP

万方数据 万方数据 基于 EDA 工具的标准单元低功耗设计方法研究 A Study of Low Power Methodology of Standard Cell based on EDA tools Abstract Along with the development of technology, advanced techniques for integrated circuits processing continually reduce the size of integrated circuits and increase its integration. But, wasted power percentage in total power dissipation continually increases with techniques scaling. When the design steps into nanoscale world, more than 50% or even higher percentage of total power dissipation is due to leakage power in wasted power. Therefore, low- leakage power design is an effective technique for controlling this problem in integrated circuits design. The methodology of standard cell based on EDA tools is most commonly used in the design of digital integrated circuit and plays a significant role in digital chips design. The chips design and application of Low-leakage power depends on the design of standard cells of the low-leakage power. Hence, how to decrease the standard cells leakage power is a valuable design. In the beginning, this paper will utilize low-leakage power of standard cell based on EDA design and generalize it into other standard cells. Then, it summarizes the design flow of low-leakage power standard cell, designs the low-leakage power performance of the standard cell based on the SMIC 130nm CMOS (SMIC13) process makes it compatible to the cell in the original cell library and provides a technical support for low- leakage-power IC designs. In accordance with technical procedure of standard cell design, this paper will discuss as the following five steps. Firstly, according to the mechanism of production of leakage power, analyzing the leakage power of standard cell in SMIC13 cell library and optimizing the circuit configuration and scale is to decrease leakage power. II 宁波大学硕士专业学位论文 Secondly, the layout of the low-leakage power cells is in the light of the modified design idea. More importantly, the design process, including height, width,