ADCLK950BCPZ-REEL7;ADCLK950BCPZ;ADCLK950PCBZ;中文规格书,Datasheet资料.pdfVIP

Two Selectable Inputs, 10 LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK950 FEATURESFEATURES FUNCTIONAL BLOCK DIAGRAMFUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs2 selectable differential inputs LVPECL 4.8 GHz operating frequency4.8 GHz operating frequency ADCLK950 Q0 75 fs rms broadband random jitter75 fs rms broadband random jitter Q0 On-chip input terminationsOn-chip input terminations 3.3 V power supply3.3 V power supply Q1 Q1 APPLICATIONSAPPLICATIONS Q2 Low jitter clock distributionLow jitter clock distribution