改良型矩阵乘法器之设计DesignofanImprovedMatrixMultiplier.PDF

改良型矩陣乘法器之設計 Design of an Improved Matrix Multiplier 鄭夢涵 杜迪榕 楊蘭超 國立暨南國際大學資工系 國立暨南國際大學資工系 國立暨南國際大學資工系 s3321525@.tw drduh@.tw .tw parallel processing architectures are mostly considered by decades. For the advance of 摘要 manufacturing technology, high clock rate processors or multiple processors are also used to speed up the 矩陣乘法是科學與工程計算中常見的運算之 computation. In this work, another approach called 一，許多人皆為了能增進其計算效率而努力。近幾 merged arithmetic is included into our parallel 十年以來，為了加速這類需要龐大計算量的運算， architecture. It dissolves the boundary between the 平行處理不外乎為最佳的選擇。隨著硬體製造技術 individual multipliers and adders to perform multiple 的進步，選擇高速的處理器或是採用多個處理器來 multiply and addition in parallel. However, none of 執行這類型的運算也非常普遍。在此篇論文中，合 the methods, which were presented previous for 併運算將被包含在平行架構中進行。合併運算打破 reducing partial product matrix, is absolutely better 個別的乘法器與加法器的界線，而將乘法與加法視 than others. This study proposes a combined method 為一體同時執行。然而，在做個別乘積項的加法 to find out the most efficient reduction. Respecting 時，並沒有任一個方法總是最好的。因此，我們提 the user’s demand is not the same all the time; our 出一個包含