毕业答辩基于WilkinsonADC的多通道模数变换ASIC的-IHEPindico.PPT

Some considerations on the CMOS sensors for CEPC MOST-2 Wei Wei CEPC-MOST 2 Mini-workshop 2017-11-23 Outline General requirement Specifications Chip architecture Overall plan of the chip design Open questions and discussion * First questions on motivations What are we going to do? To design a chip with full functionality, and to build a prototype ladder with several layers mounted Very limited time 5 years in total, 3.5 years for the chip final design Therefore: It is very unlikely that we have parallel designs (not like MOST-1) Have to be very focused on a unique chip design Chip design tasks might be divided into blocks The requirement, spec., interface of the chip have to be determined asap Real design can be initiated asap to earn time * General requirement- from CEPC MOST 1 * from Lu Y.P. Status of CEPC MOST-1 Initial sensor RD targeting on Pixel pitch ~16 μm Power consumption 100 mW/cm2 Integration time 10-100 μs CPS design More focused, with major man power All designs on Tower Jazz 0.18μm CIS process sharing tapeout with CERN and IPHC two versions of tapeouts 1st ver.: only pixel sensors, analog readout 2nd ver.: in-pixel digitization, parallel design on readout scheme rolling shutter readout (IHEP) 22μm×22μm/ async. readout (CCNU) 25μm×25μm Chip periphery: voltage DACs, readout logic, analog chain SOI design Develop in-pixel circuit for minimum layout area SOI-collaboration between IHEP KEK Two ver. of tapeouts: 16μm×16μm in-pixel discrimination * Summarize from Zhang Y.’s slides Experiences and comments from CEPC MOST-1 Pixel size Aiming for 16μm×16μm, however very challenging in the current process (not even reported worldwide) Achieved in the SOI efforts, but very little room left for any more func. Readout time Aiming for a fast readout 10us, final goal 1us? Also very challenging under the power consumption constraints Power: aiming for 50mW/cm2 as the final goal Less periphery block integrated (some are hot elements: LDO/ Interface) A brief