基于ModelSim的FFT算法的设计学士学位论文.doc

理工大学学士学位论文 PAGE \* MERGEFORMAT PAGE \* MERGEFORMAT I 基于ModelSim的FFT算法的设计学士学位论文 摘 要 快速傅立叶变换(FFT)作为时域和频域转换的基本运算，是数字谱分析的必要前提。传统的FFT使用软件或DSP实现，高速处理时实时性较难满足，因此专用集成电路(ASIC)和可编程逻辑器件(以现场可编程门阵列FPGA为代表)应运而生。速度上ASIC更占优势，但是随着点数的增加，芯片面积将迅速扩大，也就意味着成本的提高。而FPGA内部含有硬件乘法器，大量的存储单元和可编程I/O，十分适合于FFT处理器的实现，而且相对ASIC，成本低廉，可以反复编程，便于调试，也更具市场竞争力。 本文应用Verilog语言完成32点基-2复数的FFT处理系统设计，包括蝶形运算单元设计、存储单元设计、块浮点单元设计、地址产生单元设计、功能切换单元设计以及时序控制单元的设计工作。以选取的FPGA器件库为基础，使用modelsim软件进行仿真，并对结果进行分析。 关键词：快速傅立叶变换；Verilog；单元设计；modelsim仿真 PAGE \* MERGEFORMAT PAGE \* MERGEFORMAT 75 Abstract Fast Fourier Transform is a necessary precondition of digital spectral analysis as the basic computing between the time domain and frequency domain. The traditional FFT uses software or DSP to realize, which is difficult to meet real-time in high speed processing. Application specific integrated circuit (ASIC) and programmable logic device (represented by field programmable gate array, FPGA) arises at the historic moment. ASIC has the advantage in the speed, but the chip area will expand rapidly with the processing points increasing, which means the improvement of costs. While FPGA contains hardware multipliers, massive memory cells and programmable I/O, so it is very suitable for implementation of FFT processor. Therefore, FPGA is low-cost, easy to debug and can be repeatedly programmed. It has more market competitiveness. Use Verilog language completed 32 points 2 complex FFT processing system design, Including butterfly computing unit design, storage unit design, block floating-point unit design, the address generation unit design, the function switch unit design and timing control unit design work . On the basis of the selected library as the FPGA device, use the modelsim simulation software, and analyze the results. Key Words:FFT;Verilog;Unit design;modelsim simulation 目 录 TOC \o 1-3 \h \u function by certain decomposition, can expressed as a linear combination of sinusoidal function form, and the sine function in p