Lecture-4-ndash;- State- Machine- Design课件.pptVIP

Characteristic Equations S-R Latch D Latch D F/F D F/F with Enable J-K F/F T F/F Q* = S + R’ Q Q* = D Q* = D Q* = EN D + EN’ Q Q* = J Q’ + K’ Q Q* = Q’ * 。 Designing a Synchronous System Steps for designing a clocked synchronous state machine starting from a word description or specification First understand the description or specification and resolve any questions Step 1: Construct a state/output table corresponding to the description/spec. (Or create a state diagram) * 。 Example Description Design a clocked synchronous state machine with two inputs A and B, and a single output Z that is 1 if: A had the same value at each of the two previous clocks Or B has been 1 since the last time that the first condition was true Otherwise the output is 0 * 。 Evolution of a state table Figures 7-46 and 7-47 of text Set up table having columns for the relevant info. As we have 2 inputs need the 4 choices for inputs. * 。 First input What happens when first input arrives A0 – have one 0 on A A1 – have one 1 on A * 。 Second Input Now what happens when in state A0? May have a value of 0 or 1 on the next A input. New state OK OK says have 2 of the same on A * 。 Second input (cont) Now if you are in state A1 what happens at next input? * 。 The next input Now resolve state OK May have to split state OK * 。 Next input (1) Refine state OK to indicate if A is 0s or 1s * 。 Refined state OK Two 0s on the A input * 。 Refined state OK (2) Fill in state OK1 * 。 ECE 561 - Lecture 4 ECE 561 - Lecture 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lecture 4 – State Machine Design * 。 State Machine Design State Machine types and some basics State Machine Design Process State Machine Design Examples State Machine Design in the HDL world * 。 Types of state machines Mealy Machine Characterized by – Outputs are a function of both inputs and current state * 。 State Machine Types Moore machine Characterized by