密码锁的verilog代码.doc

密码锁的verilog代码 module scan_clk ( clkout ,clk ,rst ); input rst ; input clk ; wire clk ; output clkout ; reg clkout_r ; parameter period= 200000; reg [31:0] cnt; always @( posedge clk or negedge rst) //分频50Hz begin if ( !rst ) begin cnt = {31{1b0}} ; clkout_r = 0 ; end else begin cnt= cnt+1; if (cnt == (period 1) - 1) //设定周期时间的一半 clkout_r = #1 1b1; else if (cnt == period - 1) //设定的周期时间 begin clkout_r = #1 1b0; cnt = #1 b0; end end end assign clkout = clkout_r ; endmodule module key_scan ( clk ,keydrv ,rst ); input clk ; input rst ; wire clk ; output [3:0] keydrv ; wire [3:0] keydrv ; parameter s1 = 4b1110; parameter s2 = 4b1101; parameter s3 = 4b1011; parameter s4 = 4b0111; reg [3:0]current_state; reg [3:0]next_state; always @ ( posedge clk or negedge rst ) begin if ( !rst ) current_state = s1 ; else current_state = next_state ; end always @ ( current_state ) begin case ( current_state ) s1: next_state =s2; s2: next_state =s3; s3: next_state =s4; s4: next_state =s1; default: next_state =s1; endcase end assign keydrv = current_state ; endmodule `timescale 1 ms / 1 ns module mms (enter,clk, KEYO ,KEYI ,rst,DIG,Y,right,wrong,change,led_c,clr,led_clr); input enter; output right; reg right; output wrong; reg wrong; input change; output led_c; reg led_c; input clr; output led_clr; reg led_clr; input [3:0] KEYO ; //与原理图一致，是键盘输出端口给FPGA input clk ; input rst ; output [3:0] KEYI ; //与原理图一致，是FPGA输出给 键盘 wire scanclk; wire [3:0] keydrv ; reg [3:0] keyvalue; reg [7:0] temp_r; reg [3:0] scankey_o; reg [3:0] scankey_i; wire dis; output [7:0] Y; reg [7:0] Y_r; assign Y=~Y_r; output [3:0] DIG; reg [3:0] DIG; assign dis = KEYO ; reg dis_pre; assign KEYI = keydrv; scan_clk key_clk( .clk ( clk), .clkout ( scanclk) , .rst ( rst ) ); key_scan key_scan( .clk ( scanclk ) , .keydrv (keydrv) , .rst ( rst ) ); alway