FPGA硬件验证及逻辑综合-浙江大学信息与电子工程学院.pptVIP

set lib_path /home/smic/smic_40/SCC40NLL_HS_RVT_V0p1a set smic_stdlib_path ${lib_path}/synopsys/1.1v/ set smic_iolib_path /home/smic/smic_40/SP40NLLD2RN_3P3V_V0p2/syn/3p3v/ set smic_stdsymlib_path ${lib_path}/Symbol/ set search_path $search_path $smic_stdlib_path $smic_iolib_path \ $smic_stdsymlib_path set target_library [list scc40nll_hs_rvt_ff_v1p21_-40c_basic.db \ scc40nll_hs_rvt_ss_v0p99_125c_basic.db \ scc40nll_hs_rvt_tt_v1p1_25c_basic.db] set link_library [list * SP40NLLD2RN_3P3V_V0p1_ff_V1p21_-40C.db \ SP40NLLD2RN_3P3V_V0p1_ss_V0p99_125C.db \ SP40NLLD2RN_3P3V