数字集成电路--电路、系统与设计(第二版)课后练习题-第四章-导线-Chapter-4-The-Wire.pdfVIP

1 Chapter 4 Problem Set Chapter 4 Problems 1. [M, None, 4.x] Figure 0.1 shows a clock-distribution network. Each segment of the clock net- work (between the nodes) is 5 mm long, 3 μm wide, and is implemented in polysilicon. At each of the terminal nodes (such as R) resides a load capacitance of 100 fF. a. Determine the average current of the clock driver, given a voltage swing on the clock lines of 5 V and a maximum delay of 5 nsec between clock source and destination node R . For this part, you may ignore the resistance and inductance of the network b. Unfortunately the resistance of the polysilicon cannot be ignored. Assume that each straight segment of the network can be modeled as a Π-network. Draw the equivalent cir- cuit and annotate the values of resistors and capacitors. c. Determine the dominant time-constant of the clock response at node R . S Figure 0.1 Clock-distribution network. R 2. [C, SPICE, 4.x] You are designing a clock distribution network in which it is critical to mini- mize skew between local clocks (CLK1, CLK2, and CLK3). You have extracted the RC net- work of Figure 0.2, which models the routing parasitics of your clock line. Initially, you notice that the path to CLK3 is shorter than to CLK1 or CLK2. In order to compe