verilog实验60进制计数器.docVIP

module counter60(clk_in,clkout,rst,out); input clk_in,rst; output [6:0] out; output clkout; reg [6:0] out1; reg [6:0] out2; reg [3:0] cnth; reg [3:0] cntl; reg [7:0] cnt; always @(posedge clk_in) begin if(!rst) cnt=8d0; else cnt=cnt+8d1; end assign clkout=cnt[4]; always @(posedge clkout or negedge rst) begin if(!rst) {cnth,cntl}=8d0; else if(cnth==5cntl==9) {cnth,cntl}=8d0; else if(cntl==4d9) begin cntl=4d0; cnth=cnth+4d1; end else cntl=cntl+4d1; end always @(cnth) begin case(cnth) 4d0:out1=7b011_1111;//0 4d1:out1=7b000_0110;//1 4d2:out1=7b101_1011;//2 4d3:out1=7b100_1111;//3 4d4:out1=7b110_01