先进芯片封装知识介绍.ppt

PPT课件 * * Advanced Packaging Tech * PPT课件 Outline Package Development Trend 3D Package WLCSP Flip Chip Package * PPT课件 Package Development Trend * PPT课件 SO Family QFP Family BGA Family Package Development Trend * PPT课件 CSP Family Memory Card SiP Module Package Development Trend * PPT课件 3D Package 3D Package 3D Package Introduction etCSP Stack Functional Integration High Low Tape-SCSP (or LGA) S-CSP (or LGA) S-PBGA S-M2CSP Stacked-SiP 2 Chip Stack Wirebond 2 Chip Stack Flip Chip Wirebond Multi Chip Stack Package on Package (PoP) Stacking SS-SCSP(film) FS-BGA 3S-PBGA S-SBGA S-TSOP / S-QFP 3 S-CSP S-etCSP etCSP + S-CSP PS-fcCSP + SCSP PoP with interposer FS-CSP2 FS-CSP1 Paper Thin PS-vfBGA + SCSP PiP 5SCSP SS-SCSP(paste) Ultra thin Stack D2 D3 D4 D2 D2 D3 D4 D2 PoP QFN 4SS-SCSP Stacked Die Top die Bottom die FOW materil Wire TSV TSV (Through Silicon Via) A through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die. TSV technology is important in creating 3D packages and 3D integrated circuits.?A 3D package (System in Package, Chip Stack MCM, etc.) contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. In most 3D packages, the stacked chips are wired together along their edges. This edge wiring slightly increases the length and width of the package and usually requires an extra “interposer” layer between the chips. In some new 3D packages, through-silicon via replace edge wiring by creating vertical connections through the body of the chips. The resulting package has no added length or thickness. Wire Bonding Stacked Die TSV What’s PoP? PoP is Package on Package Top and bottom packages are tested separately by device manufacturer or subcon. PoP PoP PS-vfBGA PS-etCSP Low Loop Wire Pin Gate Mold Package Stacking Wafer Thinning PoP Core Technology PoP Allows for warpage reduction by utilizing fully-molded structure More compatible with substrate th