集成电路-封装和可靠性Chapter2-1-芯片互连技术.pdf

集成电路封装测试与可靠性 Chapter 2 Chip Level Interconnection 芯片互连技术 UESTC-Ning Ning 1 集成电路封装测试与可靠性 典型的IC封装工艺流程 Wire Bond Solder Plating Wafer In (WB 引线键合) (SP 锡铅电镀) Wafer Grinding Die Coating Top Mark (WG研磨) (DC 晶粒封胶/涂覆) (TM 正面印码) Wafer Saw Molding Forming/Singular (WS 切割) (MD 塑封) (FS 去框/成型) Die Attach Post Mold Cure Lead Scan (DA 黏晶) (PMC 模塑后烘烤) (LS 检测) Epoxy Curing Dejunk/Trim Packing (EC 银胶烘烤) (DT 去胶去纬) (PK 包装) UESTC-Ning Ning 2 集成电路封装测试与可靠性  电子级硅所含的硅的纯度很高，可 达 99.9999 99999 %  中德电子材料公司制作的晶棒(长度 达一公尺，重量超过一百公斤) UESTC-Ning Ning 3 集成电路封装测试与可靠性 Wafer Back Grinding  Purpose The wafer backgrind process reduces the thickness of the wafer produced by silicon fabrication (FAB) plant. The wash station integrated into the same machine is used to wash away debris left over from the grinding process.  Process Methods: 1) Coarse grinding by mechanical. (粗磨) 2) Fine polishing by mechanical or plasma etching. (细磨抛光) UESTC-Ning