Quartus中的编译设置.pptVIP

Quartus Compilation What are Compiler Settings? Compiler control information Device device options Pin assignments Level of compilation Point of compilation in hierarchy Synthesis fitting Verification Accessed via the Processing Menu Each contains a focus point (next slide) Information stored in a Compiler Settings File (.CSF) Compiler Settings Menu STATE MACHINE PROCESSING Encoding is on a machine by machine basis Each machine in the user’s design can be marked with one of the following logic options: Auto: (Default) Use predetermined algorithm that is best for Family Minimal Bits: The Compiler will force the minimum number of registers to encode the machine: No. of bits = LOG2(states) (Current MAX+plus II MAX algorithm) One-Hot: The Compiler will force a one-hot encoding for the machine. (Current MAX+plus II FLEX algorithm) User-Encoded: Use the user encoding if it is enough to decode the machine otherwise use auto encoding These options are not affected by the Pterm/LUT synthesis option TECHNOLOGY MAPPER Specifies which Technology Mapper to use: LUT PTERM ROM AUTO (PTERM or LUT) Best implementation of either PTERMS or LUT for performance Works on entire hierarchy User can choose a level if that hierarchy level and all its children will be mapped to PTERM or LUT Recommended to use for small hierarchies only Default value is LUT Implementing Product-Term Logic Logic is chosen on a hierarchical level to map to logic in product-term, LUT, or AUTO (Pterm or LUT) mode. Implementing Product-Term Mode With Quartus An entity in a design can be tagged so every instantiation of it in the design will be implemented in the same mode Stored in Assignments Technology Mapper Creating a Custom Filter 1. Select Customize 2. Click New. Name Filter and click OK. 3. Select Filter settings Assignment Organizer 2. Choose assignment and setting 1. Click to add new assignment 3. Click Add to add assignment 3 types of Logic Options - Options for Individual Nodes Only - Opti