Lec 12. Parasitic Extraction英文文献资料.pdfVIP

Advanced VLSI Circuit Analysis Lecture 12: Parasitic Extraction Graduate Course of Fudan University Hengliang Zhu, Fang Yang 1 Layout parasitics Wires are not ideal. Parasitics: – Resistance – Capacitance – Inductance Why do we care? – Impact on delay – noise – energy consumption – power distribution 2 Layout parasitics Interconnect pr oblems II: Simulation Interconnect pr oblems II: Simulation ß Delay estimation ß Delay estimation ß Signal integrity problem ß Signal integrity problem ß Crosstalk ß Crosstalk ideal ideal or or Delay Delay Signal integrity Signal integrity crosstalk crosstalk Interconnects dominate the circuit performance Funct. Spec RTL Behav. Simul. Logic Synth. Stat. Wire Model Front-end Gate-level Net. Gate-Lev. Sim. Back-end Floorplanning