Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs后期制造，17倍可接受的原始误码率增强，高可靠性固态驱动器的动态码字转换ecc方案.pdfVIP

Solid-State Electronics 58 (2011) 2–10 Contents lists available at ScienceDirect Solid-State Electronics journal homepage: www.el /locate/sse Post-manufacturing, 17-times acceptable raw bit error rate enhancement, dynamic codeword transition ECC scheme for highly reliable solid-state drives, SSDs Shuhei Tanakamaru a,⇑, Mayumi Fukuda a, Kazuhide Higuchi a, Atsushi Esumi b, Mitsuyoshi Ito b, Kai Li b, Ken Takeuchi a a Dept. of Electrical Engineering and Information Systems, University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan b SIGLEAD Inc., 1-38-10 Nakagawa-chuo, Tsuzuki-ku, Yokohama-shi, Kanagawa 224-0003, Japan a r t i c l e i n f o a b s t r a c t Article history: A dynamic codeword transition ECC scheme is proposed for highly reliable solid-state drives, SSDs. By Available online 23 December 2010 monitoring the error number or the write/erase cycles, the ECC codeword dynamically increases from 512 Byte (+parity) to 1 KByte, 2 KByte, 4 KByte. . .32 KByte. The proposed ECC with a larger codeword Keywords: decreases the failure rate after ECC. As a result, the acceptable raw bit error rate, BER, before ECC is Solid-state drive enhanced. Assuming a NAND Flash memory which requires 8-bit correction in 512 Byte codeword ECC, SSD a 17-times higher acceptable raw BER than the conventional fixed 512 Byte codeword ECC is realized NAND Flash memory