适用于扫描测试中的测试响应压缩电路设计-计算机体系结构国家重点.pdf

计算机研究与发展 ISSN1000一1239／CN11．1777／TP 277～1 JournaJ ofComputerResearchandDevelopment 42(7)：1 282，2005 适用于扫描测试中的测试响应压缩电路设计 韩银和1’2 李晓维1’2 李华伟1 1(中国科学院计算技术研究所信息网络室北京100080) 2(中国科学院研究生院北京 100039) (yinhes@ict．ac．cn) Test forScan-BasedCircuit Response Compactor HanYinhel一。LiXiaoweil，-．andLiHuaweil 、t Nett￡Jork 100080) l竹加rmation Lnbornfory，In5titMte(圩Co”lpHtingTechnozogy，chineseAc。de”ly叮Sciences，Be{jing 2(Gmd“口招Sc矗00Z 100039) o，￡如吼i”舀PAc口dPmy0，i鲫唧，＆巧i”g AbstractAnovel called is to the data sequentialcompactorAwl—compactorpresentedcompactresponse The canbeembeddedinthecircuitasa kindof test duringtesting． proposedAwl—compactor on—chip the best ratiocanbeobtainedthe resource．Dueto singleoutput，thecompaction by onthedist“butionoferrorbits scan two rulesw订lbe toaVoid analysis duringtest，thedesign proposed 2， but the 3 and odderrors not thestaticerrorbitscanceHationalso any cancellation，includingonly dynamic usedtohandlethe ofunknownbitsin errorbitscanceUations．Thesetworulescanalsobe masking response data．0neerrorbitwithoneunknownbitshouldbedetectedifthetwo rulesaresatisfied．In proposed orderto the transferlevel or netlist ofthe in generateregister designgate design compactorautomatically theconventional a basedonrandomselectionis design