四位全加器的VHDL设计说明.pptVIP

一位全加器真值表 一位全加器的逻辑表达式 S=A⊕B⊕Cin Co=AB+BCin+ACin 其中A,B为要相加的数，Cin为进位输 入；S为和，Co是进位输出； Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity fulladder Is Port(Ci,a,b : IN std_logic; s,Co : OUT std_logic); End fulladder; Architecture m1 Of fulladder Is Signal tmp: std_logic_vector(1 downto 0); Begin tmp=(0 a) + b + Ci; s=tmp(0); Co=tmp(1); End m1; 一位全加器的数据流（逻辑）描述 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity fulladder is Port (A,B,CI:in std_logic; S,CO:out std_logic); End fulladder; Architecture dataflow of fulladder is Begin S= CI xor A xor B; CO= (A and B) or (CI and A) or (CI and B); End dataflow; 一位全加器的行为描述 Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity fulladder is Port (a,b,cin: In bit; sum,cout: Out bit); End fulladder; Architecture behave Of fulladder Is Begin Process (a, b, cin) Begin If(a Or b Or cin)= ‘0’ Then sum =‘0’; cout =‘0’; Elsif (a AND b AND cin ) =’1’ Then sum =‘1’; cout =‘1’; Elsif (a XOR b XOR cin ) =’0’ Then sum =‘0’; cout =‘1’; Else sum =‘1’; cout =‘0’; End If; End Process; End behave; 4位全加器的设计，先设计4个1位的全加器，然后将低位的进位输出与高位的进位输入相连，将要进行加法运算的两个4位数的每一位分别作为每一个1位全加器的输入，进行加法运算，所有的1位全加器的输出组成一个4位数，即输入的两个4位数之和，最高位的全加器产生的进位输出即两个4位数求和的进位输出。（如图） Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity adder4 Is Port(Cin : IN std_logic; x, y : IN std_logic_vector(3 downto 0); sum : OUT std_logic_vector(3 downto 0); Cout : OUT std_logic); End adder4; Architecture ax Of adder4 Is Signal c: std_logic_vector(0 to 4); Component fulladder Port(Ci,a,b : IN std_logic; s, Co : OUT std_logic); End component; Begin c(0)=Cin; U1:fulladder Port Map(c(0),x(0),y(0),sum(0),c(