VHDL驱动四位一体数码管(我们仅仅使用了一组段选,绝无仅有).docVIP

我们仅仅使用了一组段选（绝无仅有） library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jishi is port( clk: in std_logic; --Info: Assuming node clk is an undefined clock dout: out std_logic_vector(7 downto 0); wout: out std_logic_vector(0 to 3) ); end jishi; architecture first of jishi is signal newclk :std_logic; --Info: Detected ripple clock newclk as buffer signal a :integer range 0 to 200 :=0; signal wei :integer range 0 to 2 :=0; signal count1:integer range 0 to 9 :=0; signal count2:integ