die-stacked dram caches for servers高级体系结构.pdfVIP

In Proceedings of the 40th International Symposium on Computer Architecture (ISCA 2013) Die-Stacked DRAM Caches for Servers Hit Ratio, Latency, or Bandwidth? Have It All with Footprint Cache Djordje Jevdjic Stavros Volos Babak Falsafi EcoCloud, EPFL {djordje.jevdjic, stavros.volos, babak.falsafi}@epfl.ch ABSTRACT limit the stacked DRAM capacity to levels that are far lower than what modern server workloads demand. As such, most proposals Recent research advocates using large die-stacked DRAM caches for die stacking advocate using the stacked DRAM as a cache [13, to break the memory bandwidth wall. Existing DRAM cache 22, 24]. designs fall into one of two categories — block-based and based. The former organize data in conventional blocks (e.g., There are two classes of die-stacked DRAM caches: block-based 64B), ensuring low off-chip bandwidth utilization, but co-locate and based . Block-based designs store data at a fine granular- tags and data in the stacked DRAM, incurring high lookup latency. ity (e.g., 64B) [22, 24] in order to optimize for capacity and Furthermore, such designs suffer from low hit ratios due to poor temporal locality. As such, they require a prohibitively large tag temporal locality. In