第六章指令流水线.pptVIP

Let’s follow a Load instruction down the pipeline and see how everything works. Every instruction starts at the Instruction Fetch stage which: (a) Begins slightly after the first clock tick when PC output has stabilized to its new value. (b) And ends when the output of the I-Unit is clocked into the IF/ID register. This picture shows the state of the pipeline at the end of the Ifetch stage (you are here). Let’s expand this part of the datapath and take a better look. +1 = 33 min. (Y:13) Let’s assume the Load instruction we are following is in memory location TEN, 10. So the Ifetch stage begins shortly after the first clock tick when the value 10 appears on the Program Counter register output. This is used as the address to access the Instruction Memory and at the same time it is fed to the adder so it can be increment by four. At the end of the Ifetch stage, this clock tick will clock the output of the instruction memory, which is the Load instruction, into the If/ID pipeline register. As the same time, the PC plus 4 value, that is 14 in this case, will be clocked into the PC. Notice that the picture here shows the stage of the pipeline at the END of the Ifetch stage (you are here) so the number 14, even though is already latched into the register, will not appear at the PC output until Clk-to-Q time later. Similarly, the load instruction we just clocked into the IF/ID register will NOT appear at the register output until a Clk-toQ delay after this clock. And when it appears at the IF/iD register output, we will be in the Reg/Decode stage. +2 = 35 min. (Y:15) This picture shows the state of the pipeline at the end of Load’s Reg/Decode stage. All the datapath has to do is read register (Ra and busA) R2 from the register file. As the same time, we need to pass the Immediate field of the instruction onto the next stage (ID/Exec) register because the immediate field is needed for address calculation. Let’s concentrate on the load instruction (point to the 1st