并行乘法器-南京理工大学紫金学院vhdl实验报告-eda.docVIP

EDA技术和使用 实验报告 实验名称： 并行乘法器 姓 名： 学 号： 班 级： 通信 时 间： 2013 南京理工大学紫金学院电光系 实验目的 1、学习包集和元件例化语句的使用。 2、学习FLU（全加器单元）电路的设计。 3、学习并行乘法电路的设计。 实验原理 并行乘法器的电路原理图如下图所示，主要由全加器和和门构成。 并行乘法器原理图 实验内容 and_2 library ieee; use ieee.std_logic_1164.all; entity and_2 is port (a,b:in std_logic; y:out std_logic); end and_2; architecture and_2 of and_2 is begin y = a and b; end and_2; fau library ieee; use ieee.std_logic_1164.all; entity fau is port (a,b,cin:in std_logic; s,cout:out std_logic); end fau; architecture fau of fau is begin s = a xor b xor cin; cout = (a and b)or(a and cin)or(b and cin); end fau; top_row library ieee; use ieee.std_logic_1164.all; use work.my_components.all; entity top_row is port (a:in std_logic; b:in std_logic_vector(3 downto 0); sout,cout:out std_logic_vector(2 downto 0); p:out std_logic); end top_row; architecture structural of top_row is begin U1: component and_2 port map(a,b(3),sout(2)); U2: component and_2 port map(a,b(2),sout(1)); U3: component and_2 port map(a,b(1),sout(0)); U4: component and_2 port map(a,b(0),p); cout(2) = 0;cout(1) = 0;cout(0) = 0; end structural; mid_row library ieee; use ieee.std_logic_1164.all; use work.my_components.all; entity mid_row is port (a:in std_logic; b:in std_logic_vector(3 downto 0); sin,cin:in std_logic_vector(2 downto 0); sout,cout:out std_logic_vector(2 downto 0); p:out std_logic); end mid_row; architecture structural of mid_row is signal and_out:std_logic_vector(2 downto 0); begin U1: component and_2 port map(a,b(3),sout(2)); U2: component and_2 port map(a,b(2),and_out(2)); U3: component and_2 port map(a,b(1),and_out(1)); U4: component and_2 port map(a,b(0),and_out(0)); U5: component fau port map(sin(2),cin(2),and_out(2), sout(1), cout(2)); U6: component fau port map(sin(1),cin(1),and_out(1), sout(0), cout(1)); U7: component fau port map(sin(0),cin(0),and_out(0), p, cout(0)); end structural; lower_row library ieee; use ieee.std_logic_1164.all; u