实验四多路复用器与比较器的设计与仿真.docxVIP

实验四多路复用器与比较器的设计与仿真 一、 实验冃的： 实现多路复用器与比较器的设计与仿真。 二、 实验内容 用逻辑图设计四选一多路复用器，再用VHDL语言设计参数化 的多路复用器； 用逻辑图设计7485比较器，再用VHDL语言设计4位比较器。 8-3优先编码器。 三、 实验步骤。 （一）、多路复用器、7485比较器的逻辑图及逻辑表达式。 1?多路复用器: 逻辑框图： 1 i i i 1 1 Y ■ y -Q nV ^.nv s nV - 7485 t~ AO r s T - I s ——A2 ALBO T B2 AEBO A3 AGBO 7 s T A T A? 工 AGB- 亍 COMPARATOR 逻辑图: (-)用VHDL语言设计多路复用器、7485比较器。 1?多路复用器： LIBRARY IEEE; USE IEEE.STD LOGIC 1164.ALL; ENTITY duolu IS PORT (a: IN STD_LOGIC_VECTOR(1 DOWNTO 0); c0,cl,c2,c3: IN STD_LOGIC; y :OUT STD_LOGIC); END duolu; ARCHITECTURE arch OF duolu IS BEGIN with A select y= cOWHEN ”00”, cl WHEN 01”, c2 WHEN IO, c3 WHEN lln, O WHEN OTHERS; END arch; 2. 7485比较器: 1i brary i eee; use ieee. std_logic_1164.dll; entity bijiaoqi is port ( agbl, albl, aebl:in std logic; aO, al, a2, a3: in std_logic; bO, bl, b2, b3: in std logic; albo, aebo, agbo:out std logic); end bi jiaoqi; architecture bhv of bijiaoqi is begin process (albl, aebl, agbl, aO, al, a2, a3, bO, bl, b2, b3) beg in if (a3b3)then agbo=，r ;albo=，O ;aebo=，O; else if(a3b3) then agbo=，O ;albo=，1’ ;aebo=，O; else if(a3=b3 and a2b2 )then agbo=，r ; al bo〈二O ;aebo=，0，; else if (a3=b3 and a2b2 )then agbo〈二O ;albo=，1 ;aebo=，O; else if (a3=b3 and a2=b2 and albl)then agbo=，1 ;albo=，O ;aebo=，O; else if(a3=b3 and a2=b2 and albl)then agbo=，0，;albo=，1 ;aebo=，O; else if(a3=b3 and a2=b2 and al=bl and aObO)then agbo=，1 ;albo=，O ;aebo=，O; else if(a3=b3 and a2=b2 and al二bl and aObO)then agbo=，0J ; al bo〈二’r ;aebo=，0，; else if(a3=b3 and a2=b2 and al=bl and aO=bO and acbl=， T)then agbo〈二O ;albo=，O ;aebo=，1; else if (a3=b3 and a2=b2 and al=bl and aO=bO and agbl=，1 and albl=，O and aebl=，O) then agbo=，r ; al bo〈二O ;aebo=，0，; else if (a3=b3 and a2=b2 and al二bl and aO=bO and agbl=，O and albl=，T and aebl=，O) then agbo=，O ;albo=，1’ ;aebo=，O; else if (a3=b3 and a2=b2 and al二bl and aO=bO and agbl二1 and albl二’1 and aebl二O)then agbo=，0，;albo=，O ;aebo=，O; else if (a3=b3 and a2=b2 and al=bl and aO=bO and agbl=，O and albl=，0, and aebl=，0,) then agbo=，1 ;albo=，1’ ;aebo=，O;