数字集成电路部分课后习题chapter10_ex.pdfVIP

1 Chapter 10 Problem Set Chapter 10 PROBLEMS 1. [C, None, 9.2] For the circuit in Figure 0.1, assume a unit delay through the Register and Logic blocks (i.e., tR = tL = 1). Assume that the registers, which are positive edge-triggered, have a set-up time t of 1. The delay through the multiplexer t equals 2 t . S