基于人文价值的旅游小镇设计研究.pptVIP

ITO薄膜晶体管辅助层的文献调研 薄膜晶体管与先进显示技术实验室 姓名：刘洋 学号：1101213713 研究小组：TFT一组 Thin Film Transistor and Advanced Display Lab 组会汇报 文献调研 实验进展 下一步实验计划 汇报内容 文献调研 实验进展 下一步研究计划 文献调研背景 目前在实验室制备的ITO TFT器件中，迁移率不高~10cm2/vs，且有源层厚度在10nm左右，厚度太薄易产生其他问题，如不同区域器件特性不均匀，实验可重复性差；另一方面，实验证实IGZO作为辅助层的ITO TFT迁移率有所提高 ，因此希望找到其他的辅助层材料实现调节阈值电压，提高迁移率的作用，比如ZTO。 图1 ITO TFT Id-Vg转移特性图 图2 ITO/IGZO TFT Id-Vg转移特性图 文献调研 实验进展 下一步研究计划 文献调研一 器件结构：Bottom gate structure 工艺流程：Mo栅 SiO2栅介质：PECVD 380℃，120nm ITO层：O2/[Ar+O2]=44%，0.26Pa，DC power density 2.2W/cm2 ZTO层：~Zn:Sn=70:30，magnetron sputter The active area was defined using a shadow mask during deposition of the ZTO/ITO film.(W/L=1000 μm/15 μm) ITO源/漏：DC sputter 退火：空气中1h 500℃ Ji-In Kim, K.H. Ji, H. Y. Jung, etc,” Improvement in both mobility and bias stability of ZnSnO transistors by inserting ultra-thin InSnO layer at the gate insulator/channel interface”, Applied Physic Letters 99, 122102 (2011). 文献调研 实验进展 下一步研究计划 文献调研一 FIG. 3. (Color online) Evolution of the transfer characteristics of the (a) ZTO and (b) ZTO/ITO (3.5 nm) devices as a function of the negative bias stress (-BS) time, and (c) ZTO and (d) ZTO/ITO (3.5 nm) devices as a function of the positive bias stress (+BS) time “The interfacial ITO layer not only provides a fast carrier path but also reduces the interfacial trap density.” Ji-In Kim, K.H. Ji, H. Y. Jung, etc,” Improvement in both mobility and bias stability of ZnSnO transistors by inserting ultra-thin InSnO layer at the gate insulator/channel interface”, Applied Physic Letters 99, 122102 (2011). 文献调研 实验进展 下一步研究计划 文献调研一 FIG. 4. (Color online) (a) The +BS and -BS-induced Vth variations for the ZTO/ITO devices with increasing ts. The evolution of the Vth variations for the (b) reference and (c) optimal bi-layer devices under thermal stress from 298 to 378 K. (d) EA as a function of V