D系统设计_徐向民_第三章组合逻辑电路.pptVIP

3.4 其它组合逻辑模块 多路选择器 多路选择器的逻辑功能是在地址选择信号的控制下，从多路输入数据中选择一路数据作为输出端口的输出数据. 4选1多路选择器 Library IEEE; Use IEEE.std_logic_1164.all; Entity mux4 is port ( input : in std_logic_vector (3 downto 0 ); a, b: in std_logic; y: out std_logic ); End mux4; Architecture behav of mux4 is signal sel :std_logic_vector(1 downto 0); Begin sel=b a; process(input , sel) begin 信号需在结构体中说明，而变量可在进程中说明。 P48 4选1多路选择器 if (sel=“00”) then y=input(0); elsif (sel=“01”) then y=input(1); elsif (sel=“10”) then y=input(2); elsif (sel=“11”) then y=input(3); else y=‘Z’; end if; End process; End behav; P48 求补器 Library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.std_logic_unsigned.all; Entity hosuu is port ( a : in std_logic_vector ( 7 downto 0 ) ; b : out std_logic_vector ( 7 downto 0) ); End hosuu; Architecture rtl of hosuu is Begin b= not a +‘1’; End rtl; P46 三态门 Library IEEE; Use IEEE.std_logic_1164.all; Entity tri_gate is port ( din , en : in std_logic; dout : out std_logic ); End tri_gate ; Architecture behav of tri_gate is Begin process ( din ,en) begin if (en=‘1’) then dout=din; else dout=‘Z’; end if ; end process; End behav; 采用防护式块语句来表示三态门： Architecture blk of tri_gate is Begin tri_gate2: block (en=‘1’) begin dout=guarded din; end block; End blk; P46 单向总线缓冲器 Library IEEE; Use IEEE.std_logic_1164.all; Entity tri_buf8 is port ( din : in std_logic_vector(7 downto 0) ; en : in std_logic ; dout : out std_logic_vector(7 downto 0) ); End tri_buf8 ; Architecture behav of tri_buf8 is Begin process ( din ,en) begin if (en=‘1’) then dout=din; else dout=“ZZZZZZZZ”; end if ; end process; End behav; P46 双向总线缓冲器 Library IEEE; Use IEE