数字设计基础双语课件（第10章）.pptVIP

10.2 The dataflow description 1. Local signals Full adder circuit with the internal nodes n1, n2, n3, n4 are the internal nodes of the circuit * 10.2 The dataflow description ARCHITECTURE number3 OF fulladd IS SIGNAL n1, n2, n3, n4: STD_LOGIC; BEGIN n1 = x XOR y; sum = cin XOR n1; n2 = x AND y; n3 = cin AND x; n4 = y AND cin; cout = n2 OR n3 OR n4; END ARCHITECTURE number3; the VHDL description is changed to Local signals n1, n2, n3 and n4 as part of the description * 10.2 The dataflow description 2. Concurrent processing ARCHITECTURE number3 OF fulladd IS SIGNAL n1, n2, n3, n4: STD_LOGIC; BEGIN n1 = x XOR y; sum = cin XOR n1; n2 = x AND y; n3 = cin AND x; n4 = y AND cin; cout = n2 OR n3 OR n4; END ARCHITECTURE number3; Let’s Consider the two descriptions （1） * 10.2 The dataflow description ARCHITECTURE number4 OF fulladd IS SIGNAL n1, n2, n3, n4: STD_LOGIC; BEGIN sum = cin XOR n1; cout = n2 OR n3 OR n4; n1 = x XOR y; n2 = x AND y; n3 = cin AND x; n4 = y AND cin; END ARCHITECTURE number4; （2） * 10.2 The dataflow description Although they are written in a different order, they do exactly the same thing. Unlike programming languages, VHDL normally monitors all statements at the same time, and executes a statement when one of its right hand side (RHS) values changes. This is called concurrent execution. Concurrent execution * 10.2 The dataflow description 3. Dataflow VHDL In the jargon of VHDL, the style of coding that the outputs and inputs are related through Boolean or arithmetic operators and all statements operate concurrently, is called dataflow. * 10.3 Structural VHDL 1. The work library When designs are compiled they are placed into a library ready to be used by other designs. By default, the current working library is called work. When compiled, it is added to the work library. ARCHITECTURE simple OF fulladd IS BEGIN sum = cin XOR x XOR y; cou