VHDL音乐播放器源代码.docVIP

下载可编辑 .专业.整理. 4m分频 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div4 is port(clk_in : in std_logic; clk_out : out std_logic); end; architecture a of div4 is signal cnt : integer range 0 to 6; signal clk_tmp : std_logic; begin process(clk_in) begin if (clk_inevent and clk_in=1) then if cnt=6 then cnt=0; clk_tmp= not clk_tmp; else cnt=cnt+1; end if; end if; end process; clk_out=clk_tmp; end; 4分频 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity div4m is port(clk_in : in std_logic; clk_ou