《基于QuartusII的FPGACPLD数字系统设计与应用》范例的源程序文件.doc

. . . . 2-28 module adder_4(cout,sum,ina,inb,cin,clk); output[3:0] sum; output cout; input[3:0] I na,inb; //tempa，tempb中间变量声明 input cin,clk; reg[3:0] tempa,tempb,sum; reg cout; reg tempc; //tempc中间变量声明 always @(posedge clk) //always clk上升沿触发 begin //阻塞语句 tempa=ina; tempb=inb; tempc=cin; end always @(posedge clk) //always clk上升沿触发 begin {cout,sum}=tempa+tempb+tempc; end endmodule 2-40 `timescale 1ns/10ps module adder4_testbench; reg [3:0] ina,inb; reg cin; reg clk=0; wire [3:0] sum; wire cout; always #10 clk=~clk; initial begin ina=0; repeat(20) #20 ina =$random; //随机数ina产生 end initial begin inb=0; repeat(10) #40 inb =$random; //随机数inb产生 end initial begin cin=0; repeat(2) #200 cin ={$random}%16;// 随机数inc产生 #200 $stop； end adder4 adder4_te( .clk (clk ), .sum ( sum ), .cout ( cout), .ina ( ina ), .inb ( inb ), .cin ( cin ) ); initial endmodule 2-73 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SEG_7 IS PORT (SEG: IN STD_LOGIC_VECTOR(3 DOWNTO 0 ); //--四位二进制码输入 Q3: OUT STD_LOGIC_VECTOR(6 DOWNTO 0) );//--输出LED七段码 END SEG_7; ARCHITECTURE ART OF SEG_7 IS BEGIN PROCESS(SEG) BEGIN CASE SEG IS WHEN 0000 = Q3=0000001;--0 WHEN 0001 = Q3=1001111;--1 WHEN 0010 = Q3=0010010;--2 WHEN 0011 = Q3=0000110;--3 WHEN 0100 = Q3=1001100 ; --4 WHEN 0101 = Q3=0100100;--5 WHEN 0110 = Q3=0100000;--6 WHEN 0111 = Q3=0001111;--7 WHEN 1000 = Q3=0000000;--8 WHEN 1001 = Q3=0000100;--9 WHEN OTHERS = Q3=1111111; END CASE; END PROCESS; END ART; 3-1 `timescale 1ns/1ns module Decoder2x4(A,B,EN,Z) ; input A,B,EN; output [0:3] Z; wire Abar, Bbar; assign #1 Abar=~A; // 语句1 assign #