数字逻辑设计及运用8-1 时序电路的设计实践.pptVIP

c h a p t e r 8Sequential Logic DesignPractices时序逻辑设计实践 数字逻辑设计及应用 Chapter 8 8.1 Sequential Circuit Documentation Standards(时序电路文档标准) 8.1.4 Timing Diagrams (定时图) and Specifications 8.2 Latches and Flip-Flops 8.2.1 SSI Latches and Flip-Flops(SSI型锁存器和触发器) applications： 8.2.2 Switch Debouncing开关消抖、 8.2.4 Bus Holder Circuit总线保持 8.2.5 Multibit Registers and Latches多位寄存器和锁存器 Hold-time margin Setup-time margin 8.2 Latches and Flip-Flops( 锁存器和触发器) SSI Latches and Flip-Flops D Latches Switch Debouncing (开关消抖) Push (开关闭合) Push (开关闭合) Ideal Case (理想情况) 0 0 1 1 Push (开关闭合) 0 0 1 1 Push (开关闭合) why this circuit should not be used with the high-speed CMOS devices? (为什么不应该同高速CMOS器件一起使用？) Bus Holder Circuit (总线保持电路) SDATA 4-bit Register(4位寄存器74x175) 6位寄存器74x174 8-bit Register 74x374（三态输出） 74x377（Clock Enable, 时钟使能） register and latch 寄存器：edge trigger chracterastic 边沿触发特性 锁存器：C有效期间输出跟随输入变化 8.4 Counters (计数器) Counter(计数器)(P710) The name counter is generally used for any clocked sequential circuit whose state diagram contains a single cycle, as in Figure 8-26. The modulus of a counter is the number of states in the cycle. A counter with m states is called a modulo-m counter or, sometimes, a divide-by-m counter. A counter with a nonpower-of-2 modulus has extra states that are not used in normal operation. 计数器的分类 按时钟：同步、异步 按计数方式：加法、减法、可逆 按编码方式：二进制、十进制BCD码、循环码 计数器的功能 计数、分频、定时、产生脉冲序列、数字运算 本节内容 行波计数器、同步计数器 MSI型计数器及其应用 二进制计数器状态的译码 8.4.1 Ripple Counters AN n-bit binary counter can be constructed with just n flip-flops and no other components , for any value of n. 2bits binary counter’s normal binary counting sequence is 00-01-10-11-00 1 0 1 0 8.4.1 Ripple Counters when a particular bit changes from 1 to 0, it generates a carry to the next most significant bit. The counter is called a ripple counter because the carry information ripples from the less significant bits to the more significant bits, one bit at a time. 00-01-10-11-00 8.4.1 Ripple Count