计算机组织与结构：版7-12_Processor Structure and Function.pptVIP

William Stallings Computer Organization and Architecture7th Edition Chapter 12 CPU Structure and Function Key terms instruction cycle instruction pipeline instruction prefetch pipeline instruction pipeline condition code flag branch prediction branch prediction delayed branch program status word (PSW) CPU Structure CPU must: Fetch instructions Interpret instructions Fetch data Process data Write data CPU With Systems Bus CPU Internal Structure Registers CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs One of the major design decisions Top level of memory hierarchy User Visible Registers General Purpose Data Address Condition Codes General Purpose Registers (1) May be true general purpose May be restricted May be used for data or addressing Data Accumulator Addressing Segment General Purpose Registers (2) Make them general purpose Increase flexibility and programmer options Increase instruction size complexity Make them specialized Smaller (faster) instructions Less flexibility Specialized 英音：[spe??laizd] 1.特化 2.专门 1.专门的，专用的 How Many GP Registers? Between 8 - 32 Fewer = more memory references More does not reduce memory references and takes up processor real estate See also RISC Estate 英音：[isteit] 屋 ；产业 How big? Large enough to hold full address Large enough to hold full word Often possible to combine two data registers C programming double int a; long int a; Condition Code Registers Sets of individual bits e.g. result of last operation was zero Can be read (implicitly) by programs e.g. Jump if zero Can not (usually) be set by programs individual英音：[,individju?l]个别的，个人的，单独的 Control Status Registers Program Counter (PC) Instruction Decoding Register (IDR) Memory Address Register (MAR) Memory Buffer Register (MBR) Revision: what do these all do? Revision 复习 Program Status Word (PSW) A set of bits Includes Condition Codes Sign of last result Zero Carry Equal