fpga可编程逻辑器件芯片ep4sgx290kf43c2n中文规格书.docxVIP

Table 1-17. Clock Resource Availability in Stratix II and Stratix II GX Devices (Part 2 of 2) Description Stratix II Device Availability Stratix II GX Device Availability Power-down mode Global clock networks, regional clock networks, dual-regional clock region GCLK, RCLK networks, dual-regional clock region Clocking regions for high fan-out applications Quadrant region, dual-regional, entire device via global clock or regional clock networks Quadrant region, dual-regional, entire device via GCLK or RCLK networks Global Clock Network Global clocks drive throughout the entire device, feeding all device quadrants. All resources within the device IOEs, adaptive logic modules (ALMs), digital signal processing (DSP) blocks, and all memory blocks can use the global clock networks as clock sources. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed by an external pin. Internal logic can also drive the global clock networks for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 1-39 shows the 16 dedicated CLK pins driving global clock networks. Figure 1-39. Global Clocking Note (1)CLK12-15CLKO-3CLK8-11Note to Figure 1-39. Global Clocking Note (1) CLK12-15 CLKO-3 CLK8-11 Note to Figure 1-39: (1) Stratix II GX devices do not have PLLs 3,4,9, and 10 or clock pins 8, 9,10, and 11. Table 5-47. EP2S15 Row Pins Global Clock Timing Parameters Parameter Minimum Timing -3 Speed Grade -4 Speed Grade -5 Speed Grade Unit Industrial Commercial tciN ns tcOUT ns tpLLCIN ns tpLLCOUT ns EP2S30 Clock Timing Parameters Tables 5-48 through 5-51 show the maximum clock timing parameters for EP2S30 devices. Table 5-48. EP2S30 Column Pins Regional Clock Timing Parameters Parameter Minimum Timing -3 Speed Grade -4 Speed Grade -5 Speed Grade Unit Industrial Commercial tciN ns tcOUT ns tpLLCIN ns tpLLCOUT ns Table 5-49. EP2S30 Column Pins Global Clock Timing