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Refer to Reading from the Dynamic Reconfiguration Interface for details. Related Information Reading from the Dynamic Reconfiguration Interface on page 159 7.. Arbitration 7. . Arbitration Figure 101. Arbitration The arbitration logic allows multiple masters to control the Avalon memory-mapped interface bus. The following feature blocks can access the programmable registers: Embedded reconfiguration streamer NPDME User reconfiguration logic connected to the reconfiguration interface These feature blocks arbitrate for control over the programmable space of each transceiver channel. Each of these feature blocks can request access to the programmable registers of a channel by performing a read or write operation to that channel. For any of these feature blocks to be used, you must first have control over the internal configuration bus. The embedded reconfiguration streamer has the highest priority, followed by the reconfiguration interface, followed by the NPDME. When two feature blocks are trying to access the same transceiver channel on the same clock cycle, the feature block with the highest priority is given access. The only exception is when a lower priority feature block is in the middle of a read/write operation and a higher priority feature block tries to access the same channel. In this case, the higher-priority feature block must wait until the lower-priority feature block finishes the read/write operation. Note: When you enable NPDME in your design, you must either: Connect an Avalon memory-mapped interface master to the reconfiguration interface. Connect the reconf igclock and reconf igreset ports, and ground the reconfigwritez reconfigreadz reconfigaddress,and reconf igwr it edata ports of the reconfiguration interface. If you do not connect the reconfiguration interface signals appropriately, the NPDME does not function properly. Recommendations for PMA Dynamic Reconfiguration Some PMA features that can be dynamically reconfigured, like the reference cloc