fpga可编程逻辑器件芯片ep4sgx290kf40i4n中文规格书.docxVIP

Signal Name In/Out Width Description For GMII, the clock frequency is 125 MHz. For Mil, the receive clock is 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps. emacphyrxdi[7:0] PHY Receive Data In 8 This is an eight-bit receive data bus from the PHY. In GMII mode, all eight bits are sampled. The validity of the data is qualified with phyrxdvi and phyrxeri. For lower speed Mil operation, only bits [3:0] are sampled. These signals are synchronous to clkrxi. emacphyrxdvi PHY Receive Data Valid In 1 This signal is driven by PHY. In GMII mode, when driven high, it indicates that the data on the phyrxdi bus is valid- It remains asserted continuously from the first recovered byte of the frame through the final recovered byte. emacphyrxeri PHY Receive Error In 1 This signal indicates an error or carrier extension (GMII) in the received frame. This signal is synchronous to clkrxi. ema crstcl kr xno Receive clock reset output. Out 1 Receive clock reset output, synchronous to clkrxi. The reset pulse width of the rstc 1 krxno signal is three transmit clock cycles. ema cphyc r si PHY Carrier Sense In 1 This signal is asserted by the PHY when either the transmit or receive medium is not idle. The PHY de-asserts this signal when both transmit and receive interfaces are idle. This signal is not synchronous to any clock. ema cphycoli PHY Collision Detect In 1 This signal, valid only when operating in half duplex, is asserted by the PHY when a collision is detected on the medium. This signal is not synchronous to any clock. PHY Management Interface The HPS can provide support for either MDIO or I2C PHY management interfaces. MDIO Interface The MDIO interface signals are synchronous to 14mpclk in all supported modes. Note: The MDIO interface signals can be routed to both the FPGA and HPS I/O. Table 154. PHY MDIO Management Interface Signal HPS I/O Pin Name In/Out Width Description emacgmi EMACnMDI0 In 1 Management Data In. The PHY generates this signal to transfer register data during a rea