memory存储芯片pc28f00am29awlb中文规格书.docxVIP

16Gb, 32Gb, 64Gb, 128Gb Asynchronous/Synchronous NAND Read Operations READ PAGE CACHE SEQUENTIAL (31 h) The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY 二 1, ARDY =l).It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY 二 1 and ARDY = 0). To issue this command, write 31h to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register. The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logical block in the plane which the 31h command was issued. Do not issue the READ PAGE CACHE SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE CACHE LAST (3Fh) command. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after a MULTIPLANE READ PAGE operation (00h-32h, 00h-30h), the next sequential pages are read into the data registers while the previous pages can be output from the cache registers. After the die (LUN) is ready (RDY = 1,ARDY = 0), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select which cache register outputs data. Figure 52: READ PAGE CACHE SEQUENTIAL (31 h) Operation Cycle typeTCommandAddress x5 ^