水上水下施工作业通航安全.pptxVIP

水上水下施工作业通航安全会计学MotivationSignaling speeds continue to increase while interconnects change incrementally. 4-Layers boards with FR4 still rule.Solution spaces cannot shrink indefinitely.Board and silicon timings must continue to scale together.For example: The spec for PCIe Gen1 allocates 65 ps to the channel (1/3 of 2.5 GT/s timing budget).Without scaling, interconnects will take 2/3 of the Gen2 5 GT/s timing budget.We use equalization to improve timing margins.IntroductionSystems with equalization are best viewed as communications links where each block filters the signal. The signal at the receiver input is:binary 1binary 0whereht(t) = transmitter filterhc(t) = channel impulse responsen(t) = noiser(t) = received signal* = convolution operationIntroduction #2Let’s simplify things slightly by looking at the transmitter, interconnect channel, and receiver.The signal at the input to the receiver is a function of the transmitted signal and the channel insertion loss:frequency domaintime domain?We describe the channel as a band limited filter:Ideal Channel?S21(f)? is constant:zero amplitude distortionqS21(f) is a linear function of frequency:constant delay at all frequencies ? zero phase distortionResult: distortionless transmission, open data “eye.”Real Channel?S21(f)? isn’t constant:Losses increase with frequencyqS21(f) isn’t linear with frequency:er varies with frequencyResult: Amplitude and phase distortion cause “smearing” of pulses (ISI) which closes the “eye” diagram.The Ideal EqualizerThe ideal response requires an equalizer that responds as the inverse of the channel:Ideal EqualizerEqualizedWith an equalizer in the channel:The ideal response is typically not practical.Cost power constrains the design.Goal: reduce distortion to tolerable levels.[dB]Loss InterconnectChannel [GHz]fOverview of TechniquesThe equalizer may be placed anywhere in the channel.Often done at the transmitter (Tx), receiver (Rx), or both.Interconnects can contain equalizing filters, too.Pop