数字逻辑设计复习：lesson 3.pptVIP

answer 下周三见！ CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN 74x194 CLK CLR S1 S0 LIN D QD C QC B QB A QA RIN CLK CLR S1 S0 LIN RIN 移 位 寄 存 器 的 扩 展 并行输入 （8位） 并行 输出 8位 8.5.5 Shift-Register Counters(移位寄存器计数器) D0 = F ( Q0 , Q1 , … , Qn-1 ) Feedback logic D Q CK Q D Q CK Q D Q CK Q D Q CK Q CLK FF0 FF1 FF2 FF3 一般结构： 1000 0100 0001 0010 有效状态 其他状态 8.5.6 Ring Counters (环型计数器) D Q CK Q D Q CK Q D Q CK Q D Q CK Q CLK FF0 FF1 FF2 FF3 1000 0100 0001 0010 D0 D1 D2 D3 —— 非自启动的 无效状态 D0 = Qn-1 self-correcting counter self-correcting counter is designed so that all abnormal states have transitions leading to normal states. Self-correcting counters are desirable for the same reason that we use a minimal-risk approach to state assignment : If something unexpected happens, a counter or state machine should go to a “safe” state. 有效状态 无效状态 D Q CK Q D Q CK Q D Q CK Q D Q CK Q CLK FF0 FF1 FF2 FF3 1000 0100 0001 0010 D0 D1 D2 D3 self-correcting自启动的,自校正的 Self-correcting 4-bit,4 state ring counter with a single circulating 1 Q0 Q1 Q2 Q3 1 0 CLOCK Q0 Q1 Q2 Q3 1 0 1 0 0 0 Q0 Q1 Q2 Q3 RESET 载入 Q0 Q1 Q2 Q3 CLOCK 自校正的 RING COUNTER(P735) The major appeal of a ring counter for control applications is that its states appear in 1-out-of-n decoded form directly on the flip-flop outputs. That is,exactly one flip-flop output is asserted in each state. Furthermore, these outputs are “glitch free”. For the general case, an n-bit self-correcting ring counter uses an n-1-input NOR gate, and corrects an abnormal state within n - 1 clock ticks. Shift-Register Counters 一般结构： 反 馈 逻 辑 D0 = F ( Q0 , Q1 , … , Qn-1 ) 环形计数器： 1000 0100 0010 0001 最简单的：D0 = Qn-1 反 馈 逻 辑 自校正的：D0 = (Qn-2 + … + Q1 + Q0)’ 0111 1011 1101 1110 (Qn-2 · … · Q1 · Q0)’ D Q CK Q D Q CK Q D Q