ANALOG DEVICES ADSP-2184L ADSP-2185L ADSP-2186L ADSP-2187L DSP Microcomputer (Rev C, 2008年03月26日) 说明书.PDF

DSP Microcomputer ADSP-2184L/ADSP-2185L/ADSP-2186L/ADSP-2187L PERFORMANCE FEATURES SYSTEM INTERFACE FEATURES Up to 19 ns instruction cycle time, 52 MIPS sustained 16-bit internal DMA port for high-speed access to on-chip performance memory (mode selectable) Single-cycle instruction execution 4M-byte memory interface for storage of data tables and pro- Single-cycle context switch gram overlays (mode selectable) 3-bus architecture allows dual operand fetches in every 8-bit DMA to byte memory for transparent program and data instruction cycle memory transfers (mode selectable) Multifunction instructions Programmable memory strobe and separate I/O memory Power-down mode featuring low CMOS standby power dissi- space permits “glueless” system design pation with 400 CLKIN cycle recovery from power-down Programmable wait state generation condition 2 double-buffered serial ports with companding hardware Low power dissipation in idle mode and automatic data buffering INTEGRATION FEATURES Automatic booting of on-chip program memory from byte- wide external memory, for example,