数字逻辑与计算机组成 课件（机工） 第8章 中央处理器-流水线CPU.ppt

Notice that although the branch instruction is fetched during Cycle 4, its target address is NOT written into the Program Counter until the end of clock Cycle 7. Consequently, the branch target instruction is not fetched until clock Cycle 8. In other words, there is a 3-instruction delay between the branch instruction is issued and the branch effect is felt in the program. This is referred to as Branch Hazard in the text book. And as we will show in the next lecture, by clever design techniques, we can reduce the delay to ONE instruction. That is if the branch instruction in Location 12 is is