EDA电路分析和总结.docxVIP

library ieee; use ieee.std_logic_1164.all; entity D is port(x,cl:in std_logic; p,q:out std_logic); end D; architecture D_a of D is begin D:process(x,cl) begin if (cl=1) then p=x; q=not x; end if; end process D; end D_a; library ieee; use ieee.std_logic_1164.all; entity nd1 is port(a,b:in std_logic; c:out std_logic); end nd1; architecture nd1_a of nd1 is begin c=not(a and b); end nd1_a; library ieee; use ieee.std_logic_1164.all; entity nd2 is port(d,e,f:in std_logic; g:out std_logic); end nd2; architecture nd2_a of nd2 is begin g=not(d and e and f); end nd2_a; library ieee; use ieee.std_logic_1164.all; entity nd3 is port(j,k:in std_logic; l:out std_logic); end nd3; architecture nd3_a of nd3 is begin l=j xor k; end nd3_a; library ieee; use ieee.std_logic_1164.all; entity nd4 is port(m:in std_logic; n:out std_logic); end nd4; architecture nd4_a of nd4 is begin n=not m; end nd4_a; library ieee; use ieee.std_logic_1164.all; entity circuit is port(y,clk:in std_logic; z:out std_logic); end circuit; architecture circuit_a of circuit is component D is port(x,cl:in std_logic; p,q:out std_logic); end component; component nd1 is port(a,b:in std_logic; c:out std_logic); end component; component nd2 is port(d,e,f:in std_logic; g:out std_logic); end component; component nd3 is port(j,k:in std_logic; l:out std_logic); end component; component nd4 is port(m:in std_logic; n:out std_logic); end component; signal r1,r2,r3,r4,r5,r6,r7,r8,r9:std_logic; Begin U1:nd4 port map(y,r1); U2:D port map(r3,clk,r2,r3); U3:nd3 port map(r2,y,r4);  U4:nd3 port map(r6,r4,r5); U5:D port map(r5,clk,r6,r7); U6:nd2 port map(r1,r2,r6,r8); U7:nd2 port map(r7,r3,y,r9); U8:nd1 port map(r8,r9,z); end architecture circuit_a;