JXP3N10MRG_E靖芯科技 恒佳盛电子一级代理商.pdf

STBCHIP 100V N-Channel Enhancement Mode MOSFET DESCRIPTION SCHEMATIC DIAGRAM The JXP3N10MRG uses Shield Gate Trench D technology that is uniquely optimized to provide the most efficient high frequency switching performance. Both conduction and switching power losses are G minimized due to an extremely low combination of R and Q . This device is ideal for high-frequency DS(ON) g switching and synchronous rectification. S GENERAL FEATURES PIN ASSIGNMENT  ID =3.2A,VDS=100V SOT23-3L RDS(ON)(Typ.)=100mΩ@VGS=10V (TOP VIEW) D RDS(ON)(Typ.)=130mΩ@VGS=4.5V 3  High density cell design for ultra low RDS(ON)  Fully characterized avalanche voltage and current 3 N 1 0  Good stability and uniformity with high EAS  Excellent package for good heat dissipation 1 2 G S APPLICATION PACKAGE  PWM applications  Load switch  SOT23-3L ORDERING INFORMATION Part Number Storage Temperature Package Marking Devices Per Reel JXP3N10MRG -55°C to +150°C SOT23-3L 3N10 3000 ABSOLUTE MAXIMUM RATINGS (T =25℃ u