FPGA可编程逻辑器件芯片XCKU115-2FLVD1924I中文规格书.pdfVIP

Data Output Bus—DO[A|B]#:0 Table 16 shows low order address mapping for each port width. The data out bus reflects the contents of the memory cells referenced by the address bus at the last active clock edge. Table 16: Port Address Mapping During a write operation, the data out bus reflects the data Port Port in bus. The width of this bus equals the width of the port. Width Addresses The allowed widths appear in Table 15. 1 4095... 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 Inverting Control Pins 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 The four control pins (CLK, EN, WE and RST) for each port 2 2047... 07 06 05 04 03 02 01 00 have independent inversion control as a configuration 4 1023... 03 02 01 00 option. 8 511... 01 00 Address Mapping 16 255... 00 Each port accesses the same set of 4096 memory cells Creating Larger RAM Structures using an addressing scheme dependent on the width of the port. The block SelectRAM+ columns have specialized routing to allow cascading blocks together with minimal routing delays. The physical RAM locatio