EDA 课件文献等等.docxVIP

VHDL?(VHSIC?Hardware Description Language) is a?hardware description language?used in?electronic design automation?to describe?digital?and?mixed-signal?systems such as?field-programmable gate arrays?and?integrated circuits. VHDL program always include 5 parts: entity, architecture, configuration, package and library. Entity: An?entity?describes the interface and an?architecture which contains the actual implementation. PORT(端口名：模式(IN/OUT/BUFFER/INOUT) 数据类型) Std_logic is ruled by IEEE Architecture Architecture describe the entity. Configuration Use different combination of entity and architecture CONFIGURATION?配置名?OF?实体名?IS ???????FOR??为实体选配的构造体名 ???????END FOR； END?配置名； ? 举例说明： library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; ? entity counter is port (load, clear, clk : in std_logic; data_in : in integer; data_out : out integer); end counter; ? ----------------------------------------------------------------------------------- ----计数器count_255，计数范围：0～255 ----------------------------------------------------------------------------------- architecture count_255 of counter is ? begin ?process(clk,clear,load) ??????variable count:integer :=0; ?begin ??????if (clear = 1) then ??????????????count:=0; ???????elsif(load = 1)???????then ??????????????count:=data_in; ???????elsif((clkevent)and(clk = 1)and(clklast_value = 0))then ??????????????if(count = 255)then ?????????????????????count:=0; ??????????????else ?????????????????????count := count + 1; ??????????????end if; ???????end if; ? ???????data_out = count; ? ?end process; ? end count_255; ? ----------------------------------------------------------------------------------------- ----计数器count_64K，计数范围：0～65535 ----------------------------------------------------------------------------------------- architecture