Verilog硬件描述语言实验报告.pdf

硬件描述语言

实验报告

班级:2016133班

学号:201613354

姓名:齐方

目录

硬件描述语言····················································································································-·0-

实验报告································································································································-·0-

实验一简单组合逻辑设计································································································-·2-

实验二简单分频时序逻辑电路的设计············································································-·5-

实验三利用条件语句实现计数分频时序电路································································-·8-

实验四阻塞赋值与非阻塞赋值的区别·········································································-·14-

实验五用always块实现较复杂的组合逻辑电路························································-·18-

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实验一简单组合逻辑设计

一、实验目的

1.掌握基本组合逻辑电路的实现方法。

2.初步了解两种基本组合逻辑电路的生成方法。

3.学习测试模块的编写。

4了解不同层次的仿真。

二、实验内容

本次实验采用VerilogHDL语言设计一个可综合的数据比较器，其功能是比较数

据a与数据b的结果，如果两个数据相同，则输出结果1，否则给出结果0；并

写出测试模型，使其进行比较全面的测试。

三、实验步骤

1.建立工程文件，编写模块源码和测试模块,要求测试模块对源文件进行比较全

面的测试；

2.编译源码和测试模块，用测试模块对源文件进行测试，并进行仿真；

3.使用Modelsim-Altera,仿真进行两种:RTL仿真，和Gatelevel仿真，分别观

察波形，找出不同。

四、实验代码

1.模块源码

modulec1(equal,a,b);

inputa,b;

outputequal;

assignequal=(a==b)?1:0;

endmodule

2.测试代码

`timescale1ns/1ps

modulec1_vlg_tst();

rega;

regb;

wireequal;

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c1i1(

.a(a),

.b(b),

.equal(equal)

);

initial

begin

a=0;

b=0;

#100a=0;b=1;

#100a=1;b=1;

#100a=1